High Performance Simulator Analyzing the Efficient Cache Memory Simulation Behavior
Manoj Kumar Jain1, Ravi Khatwal2
1Dr Manoj Kumar Jain, Department of computer science, MLSU, Udaipur, India.
2RaviKhatwal,Department of computer science, MLSU, Udaipur, India
Manuscript received on February 06, 2013. | Revised Manuscript received on February 28, 2013. | Manuscript published on March 05, 2013. | PP: 1-6 | Volume-3 Issue-1, March 2013. | Retrieval Number: A1258033113/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: High performance is the major concern in the area of VLSI Design. Cache memory consumes the half of total power in various systems. Thus, the architecture behavior of the cache governs both high performance and low power consumption. Simulator simulates cache memory design in various formats with help of various simulators like simple scalar, Xilinx etc. This paper explores the issue and consideration involved in designing efficient cache memory and we have discussed the cache memory simulation behavior on various simulators. Memory design concept is becoming dominant; memory level parallism is one of the critical issues concerning its performance. We have to propose high performance cache simulation behavior for performance improvement for future mobile processors design and customize mobile devices.
Keywords: Application Specific Instruction Processors, Memory design, Simple scalar simulator, Xilinx, Micro wind, Top spice 8 Simulator etc.