Design of High Speed Ladner-Fischer Based Carry Select Adder
Pakkiraiah Chakali1, Madhu Kumar Patnala2

1Chakali Pakkiraiah, Electronics and Communication Engineering, Sree Vidyaniketan Engineering College, Tirupati, India.
2Madhu Kumar Patnala, Electronics and Communication Engineering, Sree  Vidyaniketan Engineering College, Tirupati, India.
Manuscript received on February 04, 2013. | Revised Manuscript received on February 27, 2013. | Manuscript published on March 05, 2013. | PP: 173-176 | Volume-3 Issue-1, March 2013. | Retrieval Number: A1339033113/2013©BEIESP
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Abstract: In this paper, we propose a high speed Carry Select Adder by replacing Ripple Carry Adders with parallel prefix adders. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adders (RCA) are usually preferred for addition of two multi-bit numbers as these RCAs offer fast design time among all types of adders. However RCAs are slowest adders as every full adder must wait till the carry is generated from previous full adder. On the other hand, Carry Look Ahead (CLA) adders are faster adders, but they required more area. The Carry Select Adder is a compromise on between the RCA and CLA in term of area and delay. CSLA is designed by using dual RCA: due to this arrangement the area and delay are still concerned factors. It is clear that there is a scope for reducing delay in such an arrangement. In this research, we have implemented CSLA with prefix adders. Prefix adders are tree structure based and are preferred to speed up the binary additions. This work estimates the performance of proposed design in terms of Logic and route delay. The experimental results show that the performance of CSLA with parallel prefix adder is faster and area efficient compared to conventional modified CSLA.
Keywords: prefix adder, CSLA, delay, Carry Operator, area-efficient.