Comparative Study of Delay and Power Dissipation of a Low Power CMOS BPSK Modulator Circuit
Sayani Palit1, Madhumita Mukherjee2
1Sayani Palit, Electronics and Communication Engineering-VLSI, Heritage Institute Of Technology, Kolkata, India.
2Madhumita Mukherjee, Electronics and Communication Engineering ,VLSI, Heritage Institute Of Technology, Kolkata, India.

Manuscript received on March 04, 2014. | Revised Manuscript received on March 03, 2014. | Manuscript published on March 05, 2014. | PP: 208-211 | Volume-4 Issue-1, March 2014. | Retrieval Number: A2163034114/2014©BEIESP
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Abstract: In this paper we have presented a BPSK modulator using low power CMOS technology. The key design issues in VLSI circuit design are power and delay. Thus in this paper we have focused on LP CMOS with different technologies(16nm, 22nm ,32nm,and 45nm) with the help of TANNER EDA Tool. The value of model parameters are used from Predictive Technology Model(PTM). The T-SPICE simulation results indicate that there is a 59% deduction in Dynamic power For 16nm technology compare to 45nm technology keeping supply voltage constant whereas there is 74.64% reduction in power delay product in 16nm technology compare to 45nm technology.
Keywords: BPSK, LP CMOS, Power dissipation, PTM.