Intelligent and Superior Vedic Multiplier for FPGA Based Arithmetic Circuits
Virendra Babanrao Magar
Mr. Virendra B. Magar, has done AMIETE degree in Electronics & Telecommunication Engineering from Institution of Electronics & Telecommunication Engineers(IETE), New Delhi
Manuscript received on June 05, 2013. | Revised Manuscript received on June 29, 2013. | Manuscript published on July 05, 2013. | PP: 31-36 | Volume-3 Issue-3, July 2013. | Retrieval Number: C1610073313/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The speed of a multiplier is very important to any Digital Signal Processor (DSPs). Vedic Mathematics is the earliest method of Indian mathematics which has a unique technique of calculations based on 16 Formulae. In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication, which strikes a difference in the actual process of multiplication itself. It enables parallel generation of partial products and eliminates unwanted multiplication steps. Multiplier architecture is based on generating all partial products and their sums in one step. Chipscope VIO is used to give random inputs of desired values by user, on which proposed Vedic multiplication is performed. The proposed algorithm is modeled using VHDL i.e. Very High Speed integrated circuit hardware description language. The propagation time of the proposed architecture is found quiet less. The Xilinx Chipscope VIO generator allows us to give the runtime inputs. The Xilinx Chipscope tool will be used to test the FPGA inside results while the logic running on FPGA. The Xilinx Spartan 3 Family FPGA development board will be used for this circuit. The proposed multiplier implemented using Vedic multiplication is efficient and competent in terms of area and speed compared to its implementation using Array and Booth multiplier architectures. The results clearly indicate that Urdhava Tiryakbhyam can have a great impact on improving the speed of Digital Signal Processors.
Keywords: Vedic Multiplier, urdhva tiryakbhayam, High Speed, Low Power, Latency.