Implementation of High Reliable Fine Grain Fault Tolerance Redundant Technique for FPGA
K. Sreelaxmi1, B. Srinivas2, M. J. C. Prasad3
1K. Sreelaxmi, Electronics and Communication Engineering, Malla Reddy engineering College, secunderabad, India.
2B. Srinivas, Electronics and Communication Engineering, Malla Reddy engineering College, secunderabad, India.
3M.J.C.prasad, Electronics and Communication Engineering, Malla Reddy engineering College, secunderabad, India.
Manuscript received on October 28, 2013. | Revised Manuscript received on November 02, 2013. | Manuscript published on November 05, 2013. | PP: 129-132 | Volume-3 Issue-5, November 2013. | Retrieval Number: E1915113513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: SRAM based FPGAs are attractive to use in space applications because of more flexibility and reprogram ability. As technology size decreases below nanometer SRAM based FPGAs are more susceptible to radiation. These effects can cause transient or permanent bit flipping on SRAM cells and respectively change the function of logic elements within FPGAs. Fault-masking methodologies are essential, because it is vital for the system to work always properly irrespective of various faults that occurs in Complex digital circuitry. Due to this fact, redundancy techniques, which target fault masking and fault tolerance are in our scope. In this project we are proposing Quadruple Force Decide Redundancy (QFDR) a new approach in fault tolerance for mitigation problems in digital circuits, as simply replicating complete systems in Triple Modular Redundancy (TMR) technique may not be sufficient anymore when especially applies to the space applications, failure rate increases because of second instance occurs before the first one recovers. It QFDR makes SRAM-based FPGAs effectively immune from SEU (Single Event Up-set) mitigation challenges. The proposed QFDR is operated at an abstraction level of CLBs of FPGA. The Quadruple Force Decide Redundancy (QFDR) is a redundant logical structure which quadruplicates logical functions and defines two different Force and Decide rules for different quadruple logic functions based on their level in design and then connects them together using special connection patterns. The complete logic of QFDR is implemented in VHDL. Modelsim Xilinx edition (MXE) will be used for simulation and functional verification. Xilinx ISE will be used for synthesis. Xilinx FPGA board will be used for testing and demonstration of the implemented system.
Keywords: SRAM based FPGA, Quadruple Force Decide Redundancy (QFDR).