FPGA Based Hardware Efficient Digital Decimation Filter for ∑-∆ ADC
Subir Kr. Maity1, Himadri Sekhar Das2
1Subir Kr. Maity, Department of ECE, Institute of Science & Technology, C. K. Town Midnapur (W), West Bengal , India.
2Himadri Sekhar Das, Department of ECE, Institute of Science & Technology, C. K. Town ,Midnapur (W), West Bengal, India.
Manuscript received on November 29, 2011. | Revised Manuscript received on December 15, 2011. | Manuscript published on January 05, 2012. | PP: 129-133 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0283111611/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper focuses on the design of a FPGA based off chip digital decimation filter for single bit sigma-delta A/D converter with medium oversampling ratio for the processing of audio signal. A second-order single-stage sigma-delta (∑-∆) modulator with single bit quantizer with oversampling ratio 96 from FALCON Instrument is used in this work as a reference modulator. To reduce hardware requirement, multiplier less FIR filter architecture used. Total three cascaded comb type filter are used for decimation and filtering purpose. Those filters are designed and simulated with MATLAB Filter Design Toolbox and finally mapped into XILINX SPARTAN-II XC2S50PQ208 series FPGA. The overall ADC gives 14 bit resolution.
Keywords: Oversampling, quantization, SNR, Sigma-Delta, Decimation, CIC Filter, FPGA.