Implementations of DPDE for Delay Locked Loop for High Frequency Clock of 2.5GHz High Speed Applications
J. Meenakshi1, G. Rakesh Chowdary2, A. L. G. N. Adityar3
1J.Meenakshi, M.tech VLSI, KL University, Vijayawada, India.
2G. Rakesh Chowdary, ECE, KL University Vijayawada, India.
3A.L.G.N.Aditya, M.tech VLSI, KL University, Vijayawada, India.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 522-527 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0640042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Variable delay elements have many applications in VLSI circuits. They are extensively used in digital delay locked loops phase locked loops (PLLs), digitally controlled oscillators (DCOs), and microprocessor and memory circuits. In all these circuits, the variable delay element is one of the key building blocks. Its precision directly affects the overall performance of the circuit. In this a new proposed digitally controlled delay element is implemented in 130nm technology for DLL Delay locked loop for higher clock rates greater than 2.5GHz. This is implemented in Micro wind tool.
Keywords: DLL, PLL, Delay element, Microprocessor, Clock frequency.