Effect of Thickness and Material on Electronic Properties of GAA-MuGFETs
Himani Malik1, Amarjeet Kaur2, Asha Lather3, V.K.Lamba4, Bhupesh Kharb5

1Er. Himani Malik, Electronics& Communication Engg., HCTM, Kaithal, India.
2Er. Amarjeet Kaur, Electronics& Communication Engg., ACME, Faridabad, India
3Er. Asha Lather, Electronics& Communication Engg., HCTM, Kaithal, India.
4Dr. V.K. Lamba, Electronics& Communication Engg., HCTM, Kaithal, India.
5Er. Bhupesh Kharb, Electronics& Communication Engg., GITM, Gurgaon, India
Manuscript received on September 01, 2012. | Revised Manuscript received on September 02, 2012. | Manuscript published on September 05, 2012. | PP: 284-286 | Volume-2 Issue-4, September 2012. | Retrieval Number: D0964082412/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: We present a CMOS compatible n-type gate-all-around (GAA) silicon nanowire (NW) MOSFETs with excellent electrostatic scaling. This paper investigates the sensitivity of gate-all-around (GAA) nanowire (NW) to process variations in silicon film thickness and material i.e. Si and Ge with multigate devices using analytical solutions of Poisson’s equation verified with device simulation Our study indicates that the GAA nanowire (NW) has the smallest threshold voltage (Vth) dispersion caused by process variations in silicon film thickness. Specifically, the GAA NW shows better immunity to channel thickness variation than multigate devices because of its inherently superior surrounding gate structure. To explore the optimum design space for (GAA) silicon nanowire (NW) MOSFETs were performed with three variable device parameters: channel width, material, and silicon film thickness. The efficiency of the GAA gate structures is shown to be dependent of these parameters.
Keywords: GAA gate FETs, MOS devices