Design of Open Core Protocol
NayabRasool Shaik1, Srikanth Pothula2
1Nayab Rasool Shaik, Electronics and Communication Engg, Jntuk, Pdah College, Vishakapatnam, India.
2Srikanth Pothula, Electronics and Communication Engg, Jntuk, Pdah College, Vishakapatnam, India.
Manuscript received on October 13, 2011. | Revised Manuscript received on October 24, 2011. | Manuscript published on November 05, 2011. | PP: 357-361 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0243101511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely the interface and the internal architecture of the bus. In this work we adopt the well-defined interface standard, the Open Core Protocol and focus on the design of the internal bus architecture. We develop an efficient bus architecture to support most advanced bus functionalities defined in open core protocol , including burst transactions, lock transactions, pipelined transactions, and out-of-order transactions. We first model and design the on-chip bus with transaction level modeling for the consideration of design flexibility and fast simulation speed. We then implement the RTL models of the bus for synthesis and gate-level simulation. Experimental results show that the proposed TLM model is quite efficient for the whole system simulation and the real implementation can significantly save the communication time.