Design of a High-Speed Matrix Multiplier Based on Balanced Word-Width Decomposition and Karatsuba Multiplication
R. L. Bhargavi1, M.Merlin Moses2, V.Karthikeyan3, C.Karthikeyan4

1R.L.Bhargavi, Lecturer’s in Einstein College of Engineering, Tirunelveli (Tamil Nadu), India.
2M.Merlin Moses, Lecturer’s in Einstein College of Engineering, Tirunelveli (Tamil Nadu), India.
3V.Karthikeyan, Lecturer’s in Einstein College of Engineering, Tirunelveli (Tamil Nadu), India.
4C.Karthikeyan, Assistant Professor in Einstein College of Engineering, (Tamil Nadu), India
Manuscript received on January 01, 2013. | Revised Manuscript received on January 02, 2013. | Manuscript published on January 05, 2013. | PP: 49-53 | Volume-2, Issue-6, January 2013. | Retrieval Number: F1088112612/2013©BEIESP
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Abstract: This paper presents a flexible 2×2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. Balanced word-width decomposition scheme is discussed, which support 2’s complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. The objective is to propose a flexible and energy efficient matrix multiplier, which can be extended to reconfigurable high speed processing implementation, using word width decomposition technique. This technique is based on divide and conquers approach. The Karatsuba multiplication is proposed in this basic approach. This Karatsuba multiplication is an efficient procedure for multiplying large numbers, which gives high speed performance than the booth multiplier.
Keywords: Balanced word-width decomposition. Field-programmable gate array (FPGA) implementation, matrix multiplier, Reconfigurable architecture.