Bit-Mask Based Compression of FPGA Bitstreams
1S.Vigneshwaran, VLSI Design, Anna University/ SNS College of Technology, Coimbatore, INDIA.
2S.Srikanth, VLSI Design, Anna University/SNS College of technology, Coimbatore, INDIA.
Manuscript received on February 04, 2013. | Revised Manuscript received on February 27, 2013. | Manuscript published on March 05, 2013. | PP: 137-141 | Volume-3 Issue-1, March 2013. | Retrieval Number: A1318033113/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, bitmask based compression of FPGA bit-streams has been implemented. Reconfiguration system uses bitstream compression to reduce bitstream size and memory requirement. It also improves communication bandwidth and thereby decreases reconfiguration time. The three major contributions of this paper are; i) Efficient bitmask selection technique that can create a large set of matching patterns; ii) Proposes a bitmask based compression using the bitmask and dictionary selection technique that can significantly reduce the memory requirement iii) Efficient combination of bitmask-based compression and G o l o m b coding of repetitive patterns.
Keywords: Bitmask-based compression, Decompression engine, Golomb coding, Field Programmable Gate Array (FPGA).