High Speed VLSI Architecture for Multilevel Lifting 2-D DWT using MIMO
Srikanth S.1, M. Jagadeeswari2

1S. Srikanth.S, ME VLSI DESIGN, Sri Ramakrishna Engineering College, Coimbatore, Tamilnadu, INDIA.
2M. Jagadeeswari, Professor & Head, M.E VLSI DESIGN , Sri Ramakrishna Engineering college, Coimbatore, Tamilnadu, INDIA.

Manuscript received on April 15, 2012. | Revised Manuscript received on April 20, 2012. | Manuscript published on May 05, 2012. | PP: 60-64 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0514032212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The Discrete Wavelet Transform (DWT) Lifting architecture is a powerful signal analysis technique for non-stationary data. High speed implementation of this architecture is a challenging task. This paper proposes an efficient multi-input/multi-output VLSI architecture (MIMO) for two-dimensional lifting-based discrete wavelet transform (DWT). Computing time for this high speed architecture is as low as N2 /M for an N X N image with controlled increase of hardware cost. M is the throughput rate. The experimental results show that proposed architecture provides high throughput and power consumption compared to the conventional architecture.

Keywords: Discrete Wavelet Transform Lifting Scheme, MIMO, Memory Buffer, SISO