Design of Phase Frequency Detector and Charge Pump for High Frequency PL
S. B. Rashmi1, Siva S. Yellampalli2

1S B Rashmi, Department of ECE, VTU extension Center, UTL Technologies Bangalore Karnataka India.
2Dr Siva S Yellampalli, Department of ECE, VTU extension Center UTL Technologies Bangalore Karnataka India.

Manuscript received on April 15, 2012. | Revised Manuscript received on April 20, 2012. | Manuscript published on May 05, 2012. | PP: 88-92 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0529042212/2012©BEIESP
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Abstract: A simple new phase frequency detector and charge pump design are presented in this paper. The proposed PFD uses only 4 transistors and preserves the main characteristics of the conventional PFD. Both PFD and charge pump are implemented using cadence 0.18 μm CMOS Process. The maximum frequency of operation is 5 GHz when operating at 1.8V voltage supply. It has free dead zone. It can be used in high speed and low power consumption applications. This makes the proposed PFD more suitable to low jitter applications.

Keywords: PFD, PLL, High speed.