Design and Verification of UART IP Core using VMM
T. Krishna Kathik1, T. Praveen Blessington2, Fazal. Noor Basha3, ALGN. Aditya4, S. R. Sastry Kalavakolanu6
1T. Krishna Karthik,is currently pursuing M.Tech in the area of VLSI in K L University, Vijayawada, AP, India.
2T. Praveen Blessington, Presently working as an Associate Professor & research scholar in Department of ECE, KL University, Guntur, Andhra Pradesh, India.
3Dr. Fazal Noorbasha, Presently working as an Assistant Professor, Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, India..
4A.L.G.N.ADITYA is currently pursuing M.Tech in the area of VLSI in K L University, Vijayawada, AP, India.
5S. R Sastry Kalavakolanu Presently he is pursuing M.Tech VLSI Design in KL University.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 437-441 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0642042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the earlier era of electronics the UART (Universal asynchronous receiver/transmitter) played a major role in data transmission. This UART IP CORE provides serial communication capabilities,which allow communication with modems or other external devices. Thiscore is designed to be maximally compatible with industry standard designs. Thekey features of this design are WISHBONE INTERFACE WITH 8- BIT OR 32-BIT selectable data bus modes. Debug interface in 32-bit data bus mode. Registerlevel and functionalcompatibility. FIFO operation. The design is verified using VMM based on system verilog. The test bench is written with regression test cases in order to acquire maximum functional coverage.
Keywords: UART,VMM,FIFO,WISHBONE INTERFACE.