Design and Functional Verification of a SPI Master Slave Core using System Verilog
K. Aditya1, M. Sivakumar2, Fazal Noorbasha3, T. Praveen Blessington4
1K. Aditya, Department of E.C.E, JNTU Niversity, Anantapur, A. P, India.
2M. Sivakumar, Department of E.C.E, Periyar University Dharmapuri, Tamilnadu, India.
3Dr. Fazal Noorbasha, Assistant Professor, Department of Electronics and Communication Engineering, KL University, Guntur, Andhra Pradesh, India.
4T. Praveen Blessington, Associate Professor & research scholar, Department of ECE, KL University, Guntur, Andhra Pradesh, India.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 558-563 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0643042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs ADCs and other. Many IC manufacturers produce components that are compatible with SPI and Microwire/plus. The SPI Master core is compatible with both protocols as master with some additional functionality. At the hosts side,the core acts like a Wishbone compliant slave device. The SPI master core consists of three parts, Serial interface, clock generator and Wishbone interface. The SPI core has five 32-bit registers through the Wishbone compatible interface. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. All transfers are full duplex transfers of a programmable number of bits per transfer(upto 64 bits).It has 8 slave select lines but only one is selected at a time. We design the SPI Master-Slave core design using system verilog and do functional verification for our design in modelsim.