2- Bit Comparator Using Different Logic Style of Full Adder
Vandana Choudhary1, Rajesh Mehra2
1Vandana Choudhary, M.E. Student Department of Electronics and Communication NITTTR, Chandigarh, India.
2Rajesh Mehra, Department of Electronics and Communication NITTTR, Chandigarh, India.
Manuscript received on April 04, 2013. | Revised Manuscript received on April 27, 2013. | Manuscript published on May 05, 2013. | PP: 277-280 | Volume-3, Issue-2, May 2013. | Retrieval Number: B1518053213/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper a new design of comparator is described with the help of Full adder which are the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper comparator are developed using various design of full adder. This will reduce the power of the comparator design. The proposed comparator has been designed using DSCH 3.1 and Microwind 3.1 at 120 nm technologies. The developed comparator with show an improvement of 25.14% in power.
Keywords: Full adder, nmos, pmos, cmos, speed, low power, less transistor count, efficiency.