Structural Level Designing of Processing Elements using VHDL
Manisha P. Khorgade1, Shweta Hajare2, P.K.Dakhole3
1Professor Manisha Khorgade, Electronics & Telecommunication Engineering Deptartment RGCER, Nagpur, India.
2Professor Shweta Hajare, Electronics Engineering Department YCCE, Nagpur, India.
3Dr.P.K.Dakhole, Electronics Engineering Department YCCE, Nagpur, India.
Manuscript received on May 03, 2014. | Revised Manuscript received on May 03, 2014. | Manuscript published on May 05, 2014. | PP: 9-13 | Volume-4 Issue-2, May 2014. | Retrieval Number: B2167054214/2014©BEIESP
Open Access | Ethics and Policies | Cite
©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: This paper involves structural design and development of processing elements using Hardware Description Language (HDL) using Altera or Xilinx softwares and implements them on Field Programmable Gate Arrays (FPGAs). In this paper, we will simulate and synthesize the various parameters of processing elements by using VHDL on Xilinx ISE 13.1 and target it for SPARTAN 6 FPGA board. The output is displayed by means of Liquid Crystal Display (LCD) interface. The state of each output bit is shown by using Light Emitting Diodes (LED). The processor can perform 2n number of operations where n is the control bit. More number of designs can be implemented on FPGA as per user’s needs.
Keywords: FPGA, XILINX ISE 13.1, SPARTAN 6.