Implementation of Fault Tolerant Method using BCH Code on FPGA
Mahadevaswamy V. P.1, Sunitha S. L.2, B. N. Shobha3

1Mahadevaswamy V P, ECE, Visvesvaraya Technological University, Mandya, India.
2Dr. Sunitha S.L., ECE, Visvesvaraya Technological University, Mandya, India.
3B.N. Shobha, ECE, Visvesvaraya Technological University, Banglore, India.
Manuscript received on September 01, 2012. | Revised Manuscript received on September 02, 2012. | Manuscript published on September 05, 2012. | PP: 180-182 | Volume-2 Issue-4, September 2012. | Retrieval Number: D0932082412/2012©BEIESP
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Abstract: The Fault tolerance degradation is the property that enables a system (often computer-based) to continue operating properly in the event of the failure of (or one or more faults within) some of its components. To designing a new 32-bit Arithmetic Logic Unit (ALU) that is secure against many attacks or faults and able to correct any 5-bit fault in any position of its 32 bits input register of ALU. Because the radiation effects on electronic circuits may cause to be inverted data bits of registers or memories. If one bit of main storage system is changed the mission of system would be completely different. The high motivation in choice of BCH (Bose, chaudhuri, and Hocquenghem) codes is that, it is able to correct multiple errors and these classes of codes are kind of powerful random error correcting cyclic codes. In comparison with area penalty methods, 32-bit fault tolerant ALU using BCH code is a better choice in terms of area as compared to Triple Modular Redundancy (TMR) and Residue code. This is due to the fault tolerant method for 32-bit ALU using TMR with single or triplicated voting need single voting scheme or tripled voter and two extra 32-bit ALU which has been increased the hardware overhead by 202% and 208% respectively. The Residue code requires hardware overhead of 148.9%. However, in comparison with T M R a n d R e s i d u e c o d e , BCH code needs the hardware overhead is 70 to 75%, which causes that the overall cost and power consumption will get reduces. Thus proposed fault tolerant hardware overhead has lower hardware and multiple error correction when compared to the other techniques.
Keywords: Fault Tolerant, BCH codes, ALU, Residue code, TMR, Encoder, Decoder, FPGA.