Performance Analysis of Full Adder & It’s Impact on Multiplier Design
Janagam.Srinivasa Rao1, Gulivindala.Suresh2
1J.Srinivasarao, Department of ECE, GMR Institute of Technology, Rajam, A.P. India.
2Gulivindala Suresh, Department of ECE, GMR Institute of Technology, Rajam, A.P. India.
Manuscript received on August 08, 2013. | Revised Manuscript received on August 27, 2013. | Manuscript published on September 05, 2013. | PP: 216-220 | Volume-3, Issue-4, September 2013. | Retrieval Number: D1833093413/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Full adder is an indispensable component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors etc. Adders are the core element of complex arithmetic operations like addition, multiplication, division, exponentiation etc. The various full adders available are conventional CMOS full adder, parallel prefix adders, hybrid full adders, mirror full adders, adders using mux and transmission gate logic. The main objective is to compare the existing full adder circuit’s performance and to design a Low Power Full Adder and to analyze its impact on 4×4 Wallace Tree Multiplier design. The design and implementation of proposed full adder and multiplier is done by using Mentor Graphics tool in 180 nm technology.
Keywords: Delay; Full adder; Low Power; Performance Analysis; Logic Impact; Wallace Tree multiplier.