Real Time Implementation of Speech Codec G.729 using CS-ACELP on TM 1000 VLIW DSP processor
Vivek Kapur1, M. M. Raghuvanshi2, A. B. Maidamwar3 

1Vivek Kapur, NYSS college of engineering, Nagpur, (Maharashtra), India.
2Dr. M. M. Raghuvanshi, NYSS College of engineering, Nagpur, (Maharashtra), India.
3A. B. Maidamwar, NYSS College of engineering, Nagpur, (Maharashtra), India.
Manuscript received on October 01, 2011. | Revised Manuscript received on October 17, 2011. | Manuscript published on November 05, 2011. | PP: 46-49 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0144081511/2011©BEIESP
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Abstract: Conjugate structure algebraic CELP (G.729) is a voice codec that compresses speech signal based on model parameter of human voice. This paper deals with implementation of a speech-coding algorithm CS-ACELP using ITU-T’s G.729 recommendation and optimize it for real-time implementation on a Very Long Instruction Word (VLIW) Digital Signal Processor (DSP) Central Processing Unit (CPU). Very long instruction word or VLIW refers to a CPU architecture designed to take advantage of instruction level parallelism (ILP). A processor that executes every instruction one after the other (i.e. a non-pipelined scalar architecture) may use processor resources inefficiently, potentially leading to poor performance.
Keywords: G.729, CS-ACELP, DSP processor.