Constant Bit Rate Traffic Investigation for Network-on-Chip
Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, Maharana Pratap University of Agriculture and Technology, Udaipur, Rajasthan, India.
Manuscript received on October 09, 2011. | Revised Manuscript received on October 24, 2011. | Manuscript published on November 05, 2011. | PP: 286-291 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0230101511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Scalable Networks on Chips (NoCs) are needed to match the ever-increasing communication demands of large-scale Multi-Processor Systems-on-chip (MPSoCs) for high-end wireless communications applications. The heterogeneous nature of on-chip cores, and the performance efficiency requirements typical of high end computing devices call for efficient NoCs architecture which eliminate much of the overheads connected with general-purpose communication architectures. This paper evaluates the performance of regular and Irregular NoC for constant bit rate traffic pattern for various routing algorithms such as X-Y, O-E, Up*/down*. The performance of NoC with varying number of cores is evaluated on the systemC based discrete event, cycle accurate NoC performance simulator.
Keywords: NoC, SoC, simulation, traffic pattern, Topology.