A Novel RISC Processor with Crypto Specific Instruction Set
Bhagyasree. P1, C. Silpa2, M. J. C. Prasad3
1Bhagyasree. P, Electronics and Communications Engineering, Malla Reddy Engineering College, Secunderabad, India.
2C. Silpa, Electronics and Communications Engineering, Malla Reddy Engineering College, Secunderabad, India.
3Dr. M.J.C.Prasad, Electronics and Communications Engineering,, Malla Reddy Engineering College, Secunderabad, India.
Manuscript received on October 23, 2013. | Revised Manuscript received on November 01, 2013. | Manuscript published on November 05, 2013. | PP: 124-128 | Volume-3 Issue-5, November 2013. | Retrieval Number: E1924113513/2013©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Old-time necessity for security and data protection against unauthorized access to classified information in many industries especially in military application is undeniably sobering. Hence, Cryptography plays a significantly important role in, the security of data transmission. On one hand, with developing computing technology, implementation of sophisticated cryptographic algorithms has become feasible. On the other hand, stronger cryptographic specifications are needed in order to be reluctant to possible threats. Some well-known examples of cryptographic algorithms are DES and AES. One of the main concerns in designing cryptographic algorithms is efficiency in either software or hardware implementation. General purpose processors are mostly used to speed up data manipulation and information processing in systems. Nevertheless, these processors are not performance efficient when they are utilized for data encryption and decryption. A novel RISC processor with Crypto Specific Instruction Set has been designed such that the processor is a Crypto Instruction-Aware RISC Processor, that makes the encryption and decryption processes of data faster, with the help of techniques like pipelining, register windows and a special architecture of barrel shifter. The main goal of this paper is to present a novel processor architecture being feasible for high speed implementation of low throughput cryptographic algorithms.
Keywords: Cryptographic Algorithms, Pipeline Technique, Register Windowing Technique, RISC Processor.