Workload Pruning for Effective Architecture Exploration
Byeong Kil Lee
Byeong Kil Lee, Department of Electronics and Communication Engineering, UCCS, 1420 Austin Bluffs Parkway, Colorado Springs, CO 80918, USA.
Manuscript received on March 02, 2019. | Revised Manuscript received on March 05, 2019. | Manuscript published on March 30, 2019. | PP: 7-17 | Volume-8 Issue-6, March 2019. | Retrieval Number: E3182018519/19©BEIESP
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Abstract: Design exploration requires the detailed simulation which is running multiple applications on a cycle-level microprocessor simulator. Main objectives of simulation-level design exploration include understanding the architectural behaviors of target applications and finding optimal configurations to cover wide range of applications in terms of performance and power. However, full simulation of an industry standard benchmark suite takes several weeks to months to complete. This problem has motivated several research groups to come up with methodologies to reduce simulation time while maintaining a certain level of accuracy. Among many techniques for reducing simulation time, a tool called SimPoint is popularly used. However, simulation load even with the reduced workloads is still heavy, considering design complexity of modern microprocessors. Motivation of this research is started from how design exploration is actually performed. Designers will observe the performance impact from resource variations or configuration changes. If a simulation point shows low sensitivity to resource variations, designers would skip those simulations. In this paper, we focus on identifying those simulation points which do not give big impact to representative behaviors, by which overall simulation time can be effectively reduced. We also performed the performance-sensitivity-based similarity analysis (K-mean clustering) among simulation points on specific performance metric which can lead to effective workload pruning. 
Keywords: Workload Characterization; Performance Evaluation; Workload Reduction; Early-Stage Design Exploration; Performance Evaluation.