Comparative Study for Delay & Power Dissipation of CMOS Inverter in UDSM Range
Jagannath Samanta1, Bishnu Prasad De2, Banibrata Bag3, Raj Kumar Maity4
1Jagannath Samanta, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
2Bishnu Prasad De, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
3Banibrata Bag, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
4Raj Kumar Maity, Electronics & Communication Engineering, Haldia Institute of Technology, Haldia, West Bengal, India.
Manuscript received on December 02, 2011. | Revised Manuscript received on December 14, 2011. | Manuscript published on January 05, 2012. | PP: 162-167 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0290111611/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Delay and power are two major issues in design and synthesis of VLSI circuits which depends on different design parameters. In this paper, the relative study of propagation delay and power consumption of UDSM CMOS inverter is found considering the channel length below 100nm. The simulation results are taken for different technology (32nm, 45nm, 65nm and 90nm) with the help of Tanner (T-spice) simulation tool. The values of model parameters are used from current Berkeley Predictive Technology Model (PTM). Also the results are analyzed by varying load capacitance, supply voltage & transistor widths.
Keywords: UDSM, T-Spice, BPTM, Delay, Power dissipation, PDP, CMOS Inverter.