Bursty Communication Performance Analysis of Network-on-Chip with Diverse Traffic Permutations
Dr. Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, MPUAT, Udaipur, India.
Manuscript received on December 17, 2011. | Revised Manuscript received on December 27, 2011. | Manuscript published on January 05, 2012. | PP: 347-351 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0341121611
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: To satisfy the increasing communication demands of complex VLSI circuits, Network on Chip (NoC) has been introduced as a new paradigm, where processing and communication can be independently catered by communication infrastructure design. Network on Chip proposes to establish a communication infrastructure for the complex VLSI circuit in such a way that communication between any nodes in the circuit is possible even if the circuit blocks are not directly connected by a direct channel. Each circuit block of the whole circuit can be assumed as an Intellectual Property (IP) which may be a microprocessor, memory or ASIC, etc. In this paper the performance of standard 2D mesh NOC is analyzed for bursty communication traffic for various traffic or topology mapping patterns such as butterfly, transpose etc over a NOC simulation framework. The routing for the NoC is assumed to be XY and OE.
Keywords: NoC, Simulation, VLSI, Transpose, Traffic latency.