Design and Simulation of Energy Efficient Full Adder for Systolic Array
Pratibhadevi Tapashetti1, A. S Umesh2, Ashalatha Kulshrestha3
1Mrs. Pratibhadevi Tapashetti is with Kruti Institute of Technology and Engineering, Raipur, India.
2Dr. A S Umesh is with Kruti Institute of Technology and Engineering , Raipur, India.
3Dr. Ashalatha Kulshrestha is with Kankeshwari Devi IT, Jamnagar, Gujarat, India.
Manuscript received on December 07, 2011. | Revised Manuscript received on December 29, 2011. | Manuscript published on January 05, 2012. | PP: 356-360 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0343121611/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Full adder is an essential component for the design and development of all types of processors viz. digital signal processors (DSP), microprocessors, Microcontrollers, ARM processors etc. Full adder is the basic building block for all arithmetic and logical operations. For the speed improvement the systolic array using the full adders is involved in almost all the processors. Adders are the core elements of complex arithmetic operations like addition, subtraction, multiplication, division, exponentiation etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. The present study proposes an efficient full adder cell design and simulation using the simulation software Edvin XP which considerably increases the speed.
Keywords: Auto Sequencing Memory(ASM),Central processing Units(CPU),Data Processing Units(DPU).