Design of RS (255, 251) Encoder and Decoder in FPGA
Anindya Sundar Das1, Satyajit Das2, Jaydeb Bhaumik3
1Anindya Sundar Das, Haldia Institute of Technology, Haldia, India.
2Satyajit Das, C R Rao Advanced Institute of Mathematics, Statistics and Computer Sciences, Hyderabad, India.
3Jaydeb Bhaumik, Haldia Institute of Technology, Haldia, India.
Manuscript received on January 01, 2013. | Revised Manuscript received on January 02, 2013. | Manuscript published on January 05, 2013. | PP: 391-394 | Volume-2, Issue-6, January 2013.
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: IDetection and correction of errors in digital data is an important issue for the modern communication systems. Therefore an efficient error control code is needed to protect the digital data. In high speed communication system Reed-Solomon codes are widely used to provide error protection especially against the burst errors. Reed-Solomon codes are cyclic, non-binary codes. In this paper RS(255, 251)encoder and decoder have been designed and implemented on an FPGA platform.
Keywords: Reed-Solomon codes, Galois field, RS encoder, RS decoder.