Study of 8 Bits Fast Multipliers for Low Power Applications
Vasudeva G1, Cyril Prasanna Raj P2
1Vasudeva G, Assistant professor, Department of ECE, Rashtreeya Vidyalaya College of Engineering, Bangalore, India.
2Dr. Cyril Prasanna Raj, P. M.S. Engineering College, Bangalore, India.
Manuscript received on February 21, 2015. | Revised Manuscript received on February 28, 2015. | Manuscript published on March 05, 2015. | PP: 1-7 | Volume-5 Issue-1, March 2015. | Retrieval Number: E1929113513/2015©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: High–speed multiplication has always been a fundamental requirement of high performance processors and systems. With MOS scaling and technological advances there is a need for design and development of high speed data path operators such as adders and multipliers to perform signal processing operations at very high speed supporting higher data rates. In Digital signal Processing applications, multiplication is one of the most utilized arithmetic operations as part of filters, convolves and transforms processors. It is found in the literature that improving multipliers design directly benefits the high performance embedded processors used in consumer and industrial electronic products. Also significant increase in the bit length increases the critical path affecting the frequency of operations. It is also found that the regular structure required for each processing elements also increases and hence consumes area and power. Hence there is a need for design and development of high-speed architectures for N-bit multipliers supporting high speed and power. In this paper we review the architecture reported in the literature for multipliers and critical issues degrading the speed and power. Based on the literature review suitable modifications are suggested in the design for high speed and low power multipliers. The multipliers Booth, Wallace tree and Dadda are implemented and the constraints Area, Power and Timing are optimized using software resources NC SIM and VC SIM.
Keywords: DSP, microprocessor, NC SIM, VC SIM