Comparative Analysis of Low Power and High Performance PTM Models of CMOS with HiK-Metal Gate Technology at 22nm
Shobha Sharma
1GShobha Sharma, ECE, Indira Gandhi Institute of Technology of GGSIP university,delhi INDIA.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 257-261 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0582042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper analysis the low power and high performance models of PTM with Hi-K metal gate cmos technology by using them in an cmos inverter at 22nm technology node.The characteristics are compared with cmos bulk technology as well. This analysis gives an insight into leakages when the input voltage is sweeping from minimum to maximum voltage.The aim of HiK metal gate technology is to reduce the leakage at sub 32nm node and is a good alternative to cmos bulk technology having high leakage and power dissipation as seen in this paper’s comparative analysis. All the simulation is done with hspice simulator at 22nm technology node with PTM models of Arizona state university.
Keywords: 22nm cmos, body biasing,Scaling issues,ptm models