22nm High K Metal Gate Inverter Comparative Analysis of Substrate Biasing Effect on Low Power and High Performance Ptm Models
1Shobha Sharma, ECE, Indira Gandhi Institute of Technology of GGSIP university,delhi INDIA.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 251-256 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0581042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper analysis the low power and high performance models of PTM with Hi-K metal gate cmos technology by using them in an cmos inverter. Also the effect of substrate body biasing is analysed on the output characteristics. The comparison tables are drawn on Voltage Transfer Characteristic in normal biasing as well as in nsubstrate and psubstrate biasing with input voltage sweeping from minimum to maximum voltage, at 22nm technology node. This analysis gives an insight into unusual leakages in the gate and supply terminal at 22nm node. All the simulations are being done with Hspice simulator using PTM models of 22nm cmos HiK-metal gate of Arizona state University, USA.
Keywords: 22nm, body biasing,BSIM473, ptm, scaling issue.