Design and Comparison of Multipliers using Different Logic Styles
Aditya Kumar Singh1, Bishnu Prasad De2, Santanu Maity3
1Aditya Kumar Singh, Electronics and communication engineering, WBUT, Haldia Institute of Technology, ICARE, Haldia, India.
2Bishnu Prasad De, Electronics and communication engineering, WBUT, Haldia Institute of Technology, ICARE, Haldia, India.
3Santanu Maity, Electronics and communication engineering, WBUT, Haldia Institute of Technology, ICARE, Haldia, India.
Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 374-379 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0621042212/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Low power VLSI circuits have become important criteria for designing the energy efficient electronic designs for high performance and portable devices .The multipliers are the main key structure for designing an energy efficient processor where a multiplier design decides the digital signal processors efficiency. In this paper, 4*4 unsigned Array and Tree multiplier architecture is being designed by using 1-bit full adders and AND2 function following various logic styles. The full adders and AND2 function have been designed using various logic styles following a unique pattern of structure to improve their performance in various means like less transistors, low power, minimal delay, and increased power delay product. The various types of adders used in our paper are complementary MOS (CMOS) logic style, complementary pass-transistor (CPL) logic style and double-pass transistor (DPL) logic style. The main objective of our work is to calculate the average power, delay and power delay product of 4*4 bit multipliers following various logic styles at 5v supply voltage at 25c temperature with 0.15um technology and simulating them with T-spice of Tanner EDA tool. An multiplier architecture is designed using full adder, half adder structure and AND2 function and then the above said various logic style adders and AND2 function are replaced in the multiplier architecture and then their outputs are generated, such that their average power, delay, and power delay product are calculated.
Keywords: Array Multipliers, Tree multiplier, Full adder, CMOS, CPL, DPL, power delay product.