Design and Functional Verification of I2C Master Core using OVM
B. Santosh Kumar1, L. Ravi Chandra2, A. L. G. N. Aditya3, Fazal Noor Basha4, T. Praveen Blessington5

1B. Santosh Kumar, VLSI, KL University, Vijayawada, India.
2L. Ravi Chandra, ECE, KL University Vijayawada, India.
3A. L. G. N. Aditya, VLSI, KL University, Vijayawada, India.
4Fazal Noor Basha, ECE, KL University Vijayawada, India.
5T. Praveen Blessington , ECE, KL University Vijayawada, India.

Manuscript received on April 11, 2012. | Revised Manuscript received on April 14, 2012. | Manuscript published on May 05, 2012. | PP: 528-533 | Volume-2 Issue-2, May 2012 . | Retrieval Number: B0641042212/2012©BEIESP
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Abstract: This paper contrasts physical implementation aspects of the protocol through a number of recent Xilinx’s FPGA families, showing up the protocol features are responsible of substantial area overhead and power overhead. These help designers to make careful and tightly tailored architecture decisions. These RTL coding is carried out for the I2C protocol using the HDL code. The verification methodology carries a important role in design of the VLSI, As the functional verification of the I2C is covered using Open Verification Methodology (OVM) which does not interfere with DUT. This verification method provides the I2C with fault free and useable for modern day applications. The OVM is carried using Questasim10.0b.

Keywords: I2C, FPGA, OVM, Functional verification, HDL.