FPGA Implementation of Optimized 4 Bit BCD and Carry Skip Adders using Reversible Gates
Manjula B.B1, Venkatesh S .Sanganal2, Hemalatha.K.N3, Ravichandra V4

Manuscript received on July 01, 2012. | Revised Manuscript received on July 04, 2012. | Manuscript published on July 05, 2012. | PP: 180-184 | Volume-2, Issue-3, July 2012. | Retrieval Number: C0751062312/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: The project proposes design of BCD adder and implementation of Carry Skip adder using the new concept of Reversible logic gate to improve the design in terms of garbage’s and area on chip. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. It is not possible to realize quantum computing without reversible logic gates. Thus, the project will provide the reversible logic implementation of the conventional BCD adder using NG and NTG gate and Carry skip adder using TSG. The proposed reversible logic implementation of the 4- bit BCD adder is optimized to obtain minimum number of reversible logic gates and minimum number of garbage outputs. This project work on t he reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible BCD adder and existing Carry skip adder are implemented in VHDL Using Xilinx ISE 10.1 tool and simulated using ModelSim SE 6.3f. Implemented on FPGA Spartan-II.

Keywords: Reversible logic, Feyman gate, NOT Gate, Fredkin Gate, TSG Gate, New Toffoli Gate, New Toffoli Gate,TS-3 Gate, NTG, BCD etc.