Design of Baugh Wooley Multiplier using HPM Reduction Tree Technique
Jipsa Antony1, Jyotirmoy Pathak2
1Jipsa Antony, Department of Electronics & Communication, Lovely Professional University, Jalandhar, Punjab, India.
2Jyotirmoy Pathak, Department of Electronics & Communication, Lovely Professional University, Jalandhar, Punjab, India.
Manuscript received on November 02, 2014. | Revised Manuscript received on November 04, 2014. | Manuscript published on November 05, 2014. | PP: 12-15 | Volume-4 Issue-5, November 2014. | Retrieval Number: D2334094414 /2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Baugh Wooley Multiplier is one of the different techniques for signed multiplication. It is not widely used. Here design and implementation of 8 bit Baugh Wooley multiplier using conventional method as well as using High Performance Multiplier Reduction tree (HPM) technique and the comparative analysis of both the design for power, delay and the area foot print has done using Cadence RTL complier 180nm process technology.
Keywords: Multiplier, Baugh Wooley, HPM, Cadence RTL