A Comparative Study: Multiplier Design using Reversible Gates logic
I. Thahirabanu1, A. Ananthi2, G. Vishnupriya3, G.Usha4
1I. Thahirabanu, Department of Electronics and Communication Engineering, SNS College of Technology, Coimbatore, Tamil Nadu.
2A. Ananthi, Department of Electronics and Communication Engineering, SNS College of Technology, Coimbatore, Tamil Nadu India.
3G. Vishnupriya, Department of Electronics and Communication Engineering, SNS College of Technology, Coimbatore, Tamil Nadu. India.
Manuscript received on August 14, 2015. | Revised Manuscript received on August 27, 2015. | Manuscript published on September 05, 2015. | PP: 103-106 | Volume-5 Issue-4, September 2015 . | Retrieval Number: D2686095415 /2015©BEIESP
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©The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/
Abstract: In this paper we propose a new concept for multiplication by using modified booth algorithm, booth multiplier & wellece tree multiplier and reversible logic function. By combining modified booth algorithm with reversible gate logic it will produces further less delay compare to all other. Addition subtraction operation are realized using reversible DKG gate. Reversible logic circuits have theoretically zero internal power dissipation because they do not lose information, the classical set of gates such as AND, OR, and XOR are not reversible. This modified booth multiplier, modified booth multiplier & wellece tree multiplier with reversible gate logic are synthesized and simulated by using Xilinx 13.2 ISE simulator.
Keywords: Reversible logic gates, reversible logic circuit, partial products, adder, multiplier, power analysis, quantum computing, Future computing, simulation outputs.