A Built-in Self-Repair Scheme for Random Access Memories with 2-D Redundancy
K. Bala Souri1, K. Hima Bindu2, K. V. Ramana Rao3

1K. Bala Souri, M. Tech, Department of  ECE, Pydah College of Engineering & Technology, India.
2K. Hima Bindu, M. Tech, Department of ECE, Pydah College of Engineering & Technology, India.
3K.V. Ramana Rao, Associate Professor & Head, Department of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on October 13, 2011. | Revised Manuscript received on October 27, 2011. | Manuscript published on November 05, 2011. | PP: 327-329 | Volume-1 Issue-5, November 2011. | Retrieval Number: E0238101511/2011©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Built-in self-repair (BISR) technique has been widely used to repair embedded random access memories (RAMs). This paper presents a reconfigurable BISR (ReBISR) scheme for repairing RAMs with different sizes and redundancy organizations. An efficient redundancy analysis algorithm is proposed to allocate redundancies of defective RAMs. In the ReBISR, a reconfigurable built-in redundancy analysis (ReBIRA) circuit is designed to perform the redundancy algorithm for various RAMs. Also, an adaptively reconfigurable fusing methodology is proposed to reduce the repair setup time when the RAMs are operated in normal mode. Experimental results show that the ReBISR scheme can achieve high repair rate (i.e., the ratio of the number of repaired RAMs to the number of defective RAMs). The area cost of the ReBISR is very small, which is only about 2.7% for four RAMs (one 4 Kbit RAM, one 16 Kbit RAM, one 128 Kbit RAM, and one 512 Kbit RAM). Moreover, the time overhead of redundancy analysis is very small. Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Efficient yield-enhancement techniques for embedded memories thus are important for SOC. In this paper we present a built-in self-repair (BISR) scheme for semiconductor memories with 2-D redundancy structures. The BISR design is composed of a built-in self-test (BIST) module and a built-in redundancy analysis (BIRA) module. Our BIST circuit supports three test modes: the 1) main memory testing, 2) spare memory testing, and 3) repair modes. The BIRA module executes the proposed redundancy analysis (RA) algorithm for RAM with a 2-D redundancy structure, i.e., spare rows and spare columns.
Keywords: Built-in self-test, built-in self-repair, built-in redundancy-analysis, memory testing, semiconductor memory.