Low Power 128-Point Pipeline FFT Processor using Mixed Radix 4/2 for MIMO OFDM Systems
K. Umapathy1, D. Rajaveerappa2

1K. Umapathy, Department of ECE, Research Scholar, JNT University, Anantapur, Andhra Pradesh, India.
2Dr. D. Rajaveerappa, Department of ECE, Professor, Loyola Institute of Technology, Chennai, Tamilnadu, India.
Manuscript received on November 01, 2012. | Revised Manuscript received on November 02, 2012. | Manuscript published on November 05, 2012. | PP: 177-179 | Volume-2 Issue-5, November 2012. | Retrieval Number: E1037102512/2012©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, an area and power efficient 128- point pipeline FFT processor is proposed for MIMO – OFDM systems based on mixed-radix 4/2 multipath delay commutator architecture (R2MDC) in terms of lower complexity and higher memory utilization. A conventional mixed radix 4/2 multipath delay commutator FFT processor will increase the hardware capacity and can be used to change the order of the input sequences. The processor is characterized with capable power-consumption for different FFT/IFFT sizes. Unlike the general mixed radix-based architectures which use a larger internal word length to achieve a high signal to noise ratio (SNR), our processor keeps the internal word length the same as the word length of the input data while adopting the block-floating point (BFP) approach to maintain the SNR. The proposed FFT processor uses different commutators which can be used to decrease the delay elements and integrate with other MIMO-OFDM processing blocks. The designed 128-point FFT processor provides 49% reduction in count of logic gates and 67% in power dissipation on 90-nm CMOS technology.