Explicit Pulse Triggered Flip Flop Design based on a Signal Feed-Through Scheme
Jyothi Bandi1, K. Rakesh2
1Jyothi Bandi, Department of Electronics and Communication Engineering, M.V.G.R. College of Engineering Vizianagaram, India.
2K. Rakesh, Department of Electronics and Communication Engineering, M.V.G.R. College of Engineering Vizianagaram, India.
Manuscript received on November 02, 2014. | Revised Manuscript received on November 04, 2014. | Manuscript published on November 05, 2014. | PP: 13-15 | Volume-4 Issue-5, November 2014. | Retrieval Number: E2414114514/2014©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper, a new explicit pulse triggered flip-flop (P-FF) design is implemented and simulated in GENERIC-TDK 130-nm technology. This explicit pulse triggered flip flop consist of a pulse generator and a true single phase clock latch based on a signal feed through scheme. The pulse generator is built with two CMOS inverters along with transmission gate logic which reduces the complexity of the circuit. The Pulse generation logic used in the explicit mode by a single pulse generator is shared for many number of flip flop at a time result in reduction of power not only this overall transistor count and delay can also been reduced. The transistor count has been reduced from 24 transistors to 16 transistors and power dissipated is 21.2133u watts. And this flip flop can achieve better D-Q delay and by using this explicit pulse triggered flip flop a synchronous counter is constructed and power dissipated is very less i.e. 19.928 nwatts.
Keywords: Flipflop , to reduce no:of transistor , delay, power