Design of Fault Tolerant Reversible Multiplier
H. P. Sinha1, Nidhi Syal2
1Dr. H. P. Sinha is a Associate Director and Head of Department of Electronics & Communication Engg., M.M.E. College, Mullana, Ambala, India.
2Nidhi Syal is with Department of Electronics & Communication, Student of M.M.E. College, Mullana, Ambala, India.
Manuscript received on November 29, 2011. | Revised Manuscript received on December 15, 2011. | Manuscript published on January 05, 2012. | PP: 120-124 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0281111611/2012©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper proposes a novel 4×4 bit reversible fault tolerant multiplier circuit which can multiply two 4-bit numbers. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed reversible multiplier is better than the existing counterparts in terms of delay & power. It is based on two concepts. The partial products can be generated in parallel using Fredkin gates and thereafter the addition is done by using reversible parallel adder designed from IG gates. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.
Keywords: Reversible logic, Parity, Fredkin gate, IG gate, Constants, Garbage, Delay.