Network-on-Chip: A New SoC Communication Infrastructure Paradigm
Naveen Choudhary

Dr. Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, MPUAT, Udaipur, India.

Manuscript received on December 09, 2011. | Revised Manuscript received on December 25, 2011. | Manuscript published on January 05, 2012. | PP: 332-335 | Volume-1 Issue-6, January 2012. | Retrieval Number: F0338121611/2012©BEIESP
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Abstract: As the feature size in deep-submicron domain is continuously shrinking and the bandwidth requirements is increasing, traditional shared-bus architecture will no longer be able to meet the requirements of System-on-Chip (SoC) implementations. Specially, inherently non-scalable nature of the shared-bus architecture as well as its power hungry nature will become the communication bottleneck in most practical applications. Network-on-Chip (NoC) communication architectures have emerged as a promising alternative to address the problems associated with on-chip buses by employing a packet-based micro-network for inter-IP communication. Some of the most important phases in designing the NoC are the design of the topology or structure of the network and setting of various design parameters (such as frequency of operation, link-width, etc). This paper surveys the various topological structures for NoC proposed in the research domain.
Keywords: NoC. SoC, Topology, Routing, Buffers, Virtual Channel.